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publication number 21527 revision d amendment 5 issue date november 1, 2006 am29f002b/am29f002nb data sheet the following document contains inform ation on spansion memory products. continuity of specifications there is no change to this data sheet as a result of offering the device as a spansion product. any changes that have been made are the result of no rmal data sheet improvement and are noted in the document revision summary. for more information please contact your local sales office for additi onal information about spansion memory solutions.
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data sheet this data sheet states amd?s current technical specifications regarding the products described herein. this data sheet may be revised by subsequent versions or modifications due to changes in technical specifications. publication# 21527 rev: d amendment: 5 issue date: november 1, 2006 am29f002b/am29f002nb 2 megabit (256 k x 8-bit) cmos 5.0 volt-only boot sector flash memory distinctive characteristics single power supply operation ? 5.0 volt-only operation for read, erase, and program operations ? minimizes system level requirements manufactured on 0.32 m process technology ? compatible with 0.5 m am29f002 device high performance ? access times as fast as 55 ns low power consumption (typical values at 5mhz) ? 1 a standby mode current ? 20 ma read current ? 30 ma program/erase current flexible sector architecture ? one 16 kbyte, two 8 kbyte, one 32 kbyte, and three 64 kbyte sectors ? supports full chip erase ? sector protection features: a hardware method of locking a sector to prevent any program or erase operations within that sector sectors can be locked via programming equipment temporary sector unprotect feature allows code changes in previously locked sectors top or bottom boot block configurations available embedded algorithms ? embedded erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors ? embedded program algorithm automatically writes and verifies data at specified addresses minimum 1,000,000 write cycle guarantee per sector 20-year data retention at 125 c ? reliable operation for the life of the system package option ? 32-pin pdip ? 32-pin tsop ? 32-pin plcc compatibility with jedec standards ? pinout and software compatible with single-power supply flash ? superior inadvertent write protection data# polling and toggle bits ? provides a software method of detecting program or erase operation completion erase suspend/erase resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation hardware reset pin (reset#) ? hardware method to reset the device to reading array data (not available on am29f002nb)
2 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet general description the am29f002b family consists of 2 mbit, 5.0 volt-only flash memory devices organized as 262,144 bytes. the am29f002b offers the reset# function, the am29f002nb does not. the data appears on dq7?dq0. the device is offered in 32-pin plcc, 32-pin tsop, and 32-pin pdip packages. this device is designed to be programmed in-system with the stan- dard system 5.0 volt v cc supply. no v pp is required for write or erase operations. the device can also be pro- grammed in standard eprom programmers. this device is manufactured using amd?s 0.32 m process technology, and offers all the features and ben- efits of the am29f002, which was manufactured using 0.5 m process technology. the standard device offers access times of 55, 70, and 90 ns, allowing high speed microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device requires only a single 5.0 volt power supply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single-power-supply flash standard . com- mands are written to the command register using standard microprocessor write timings. register con- tents serve as input to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithm?an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. device erasure occurs by executing the erase command sequence. this initiates the embedded erase algorithm?an internal algorithm that automati- cally preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether a program or erase operation is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low vcc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. this can be achieved via programming equipment. the erase suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset # pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the flash memory. (this feature is not available on the am29f002nb.) the system can place the device into the standby mode . power consumption is greatly reduced in this mode. amd?s flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection.
november 1, 2006 21527d5 am29f002b/am29f002nb 3 data sheet table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . 7 device bus operations . . . . . . . . . . . . . . . . . . . . . . 8 table 1. am29f002b/am29f002nb device bus operations . . . . . .8 requirements for reading array data . . . . . . . . . . . . . . . . . . 8 writing commands/command sequences . . . . . . . . . . . . . . . 8 program and erase operation status . . . . . . . . . . . . . . . . . . . 8 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 reset#: hardware reset pin . . . . . . . . . . . . . . . . . . . . . . . . 9 output disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. am29f002b/am29f002nb top boot block sector address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 3. am29f002b/am29f002nb bottom boot block sector address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 autoselect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. am29f002b/am29f002nb autoselect codes (high voltage method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . 10 temporary sector unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 1. temporary sector unprotect operation . . . . . . . . . . . . . .11 hardware data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 low v cc write inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 write pulse ?glitch? protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 logical inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 power-up write inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 command definitions . . . . . . . . . . . . . . . . . . . . . . 12 reading array data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 autoselect command sequence . . . . . . . . . . . . . . . . . . . . . . 12 byte program command sequence . . . . . . . . . . . . . . . . . . . 12 figure 2. program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . 13 sector erase command sequence . . . . . . . . . . . . . . . . . . . . 13 figure 3. erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 erase suspend/erase resume commands . . . . . . . . . . . . . 15 command definitions ............................................................. 16 table 5. am29f002b/am29f002nb command definitions . . . . . .16 write operation status . . . . . . . . . . . . . . . . . . . . . 17 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4. data# polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . .17 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 dq2: toggle bit ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . . . . . . . . . . 18 dq5: exceeded timing limits . . . . . . . . . . . . . . . . . . . . . . . . 18 dq3: sector erase timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5. toggle bit algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 absolute maximum ratings . . . . . . . . . . . . . . . . 21 figure 6. maximum negative overshoot waveform . . . . . . . . . . . 21 figure 7. maximum positive overshoot waveform . . . . . . . . . . . . 21 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . 21 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8. test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 key to switching waveforms . . . . . . . . . . . . . . . 24 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. read operations timings . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. reset# timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. program operation timings . . . . . . . . . . . . . . . . . . . . . 28 figure 12. chip/sector erase operation timings . . . . . . . . . . . . . 29 figure 13. data# polling timings (during embedded algorithms) . 30 figure 14. toggle bit timings (during embedded algorithms) . . . 30 figure 15. dq2 vs. dq6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16. temporary sector unprotect timing diagram (am29f002b only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17. alternate ce# controlled write operation timings . . . 33 erase and programming performance . . . . . . . 34 latchup characteristics . . . . . . . . . . . . . . . . . . . 34 tsop pin capacitance . . . . . . . . . . . . . . . . . . . . 34 plcc and pdip pin capacitance . . . . . . . . . . . . 35 data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 36 pd 032?32-pin plastic dip . . . . . . . . . . . . . . . . . . . . . . . . . 36 pl 032?32-pin plastic leaded chip carrier . . . . . . . . . . . . 37 ts 032?32-pin standard thin small package . . . . . . . . . . 38 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 39 revision a (july 1998) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 revision b (january 1999) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 revision c (november 12, 1999) . . . . . . . . . . . . . . . . . . . . . 39 revision d (november 28, 2000) . . . . . . . . . . . . . . . . . . . . . 39 revision d +1 (november 5, 2004) . . . . . . . . . . . . . . . . . . . . 39 revision d +2 (august 3, 2005) . . . . . . . . . . . . . . . . . . . . . . . 39 revision d3 (december 13, 2005) . . . . . . . . . . . . . . . . . . . . 39 revision d4 (may 17, 2006) . . . . . . . . . . . . . . . . . . . . . . . . . 39 revision d5 (november 1, 2006) . . . . . . . . . . . . . . . . . . . . . 39
4 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet product selector guide note: see ?ac characteristics? for full specifications. block diagram family part number am29f002b/am29f002nb speed option v cc = 5.0 v 5% -55 v cc = 5.0 v 10% -70 -90 max access time, ns (t acc ) 557090 max ce# access time, ns (t ce ) 557090 max oe# access time, ns (t oe ) 303035 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# ce# oe# stb stb dq0 ? dq7 sector switches reset# data latch y-gating cell matrix address latch a0?a17 n/a am29f002nb
november 1, 2006 21527d5 am29f002b/am29f002nb 5 data sheet connection diagrams 3 4 5 2 1 9 10 11 12 13 27 26 25 24 23 7 8 22 21 6 32 31 20 14 30 29 28 15 16 19 18 17 a6 a5 a4 a3 a2 a1 a0 a16 dq0 a15 a12 a7 dq1 dq2 v ss a8 a9 a11 oe# a10 ce# dq7 v cc we# dq6 a17 a14 a13 dq5 dq4 dq3 reset# 1 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 32 17 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a11 a9 a8 a13 a14 a17 we# v cc reset# a16 a15 a12 a7 a6 a5 a4 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 1 31 30 2 3 4 5 6 7 8 9 10 11 12 13 17 18 19 20 16 15 14 29 28 27 26 25 24 23 22 21 32 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a12 a15 a16 reset# v cc we# a17 dq1 dq2 v ss dq3 dq4 dq5 dq6 pdip standard tsop plcc nc on am29f002nb nc on am29f002nb nc on am29f002nb
6 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet pin configuration a0?a17 = 18 addresses dq0?dq7 = 8 data inputs/outputs ce# = chip enable oe# = output enable we# = write enable reset# = hardware reset pin, active low (not available on am29f002nb) v cc = +5.0 v single power supply (see product selector guide for device speed ratings and voltage supply tolerances) v ss = device ground nc = pin not connected internally logic symbol 18 8 dq0?dq7 a0?a17 ce# oe# we# reset# n/c on am29f002nb
november 1, 2006 21527d5 am29f002b/am29f002nb 7 data sheet ordering information standard product amd standard products are available in several packages and operating ranges. the order number (valid combi- nation) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. am29f002b/ am29f002nb t -55 p c temperature range c = commercial (0c to +70c) i = industrial (?40c to +85c) e = extended (?55c to +125c) d = commercial (0c to +70c) for pb-free package f = industrial (?40c to +85c) for pb-free package k = extended (?55c to +125c) for pb-free package pac k ag e ty pe p = 32-pin plastic dip (pd 032) j = 32-pin rectangular plastic leaded chip carrier (pl 032) e = 32-pin thin small outline package (tsop) standard pinout (ts 032) speed option see product selector guide and valid combinations boot code sector architecture t = top sector b = bottom sector device number/description am29f002b/am29f002nb 2 megabit (256 k x 8-bit) cmos flash memory 5.0 volt-only program and erase valid combinations v cc voltag e am29f002bt-55 am29f002bb-55 am29f002nbt-55 am29f002nbb-55 pc, jc, ji, ec, ei, ed, ef, pd, jd, jf 5.0 v 5% am29f002bt-70 am29f002bb-70 am29f002nbt-70 am29f002nbb-70 pc, pi, jc, ji, ec, ei, ed, ef pd, pf, jd, jf 5.0 v 10% am29f002bt-90 am29f002bb-90 am29f002nbt-90 am29f002nbb-90 pc, pi, pe, jc, ji, je, ec, ei, ee ed, ef, ek pd, pf, pk jd, jf, jk
8 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy an y addressable memory loca- tion. the register is composed of latches that store the commands, along with the address and data informa- tion needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the func- tion of the device. the appropriate device bus operations table lists the inputs and control levels required, and the resulting output. the following sub- sections describe each of these operations in further detail. table 1. am29f002b/am29f002nb device bus operations legend: l = logic low = vil, h = logic high = vi h, vid = 12.0 0.5 v, x = don?t care, din = data in, dout = data out, a in = address in note: see the sections on sector group protection and temporary sector unprotect for more information. this function requires the reset# pin and is therefore not av ailable on the am29f002nb device. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in th is mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? fo r more information. refer to the ac read operations table for timing specifica- tions and to the read operations timings diagram for the timing waveforms. i cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . an erase operation can erase one sector, multiple sec- tors, or the entire device. the sector address tables indicate the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. see the command defini- tions section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? and autoselect command sequence sections for more information. i cc2 in the dc characteristics table represents the active current specification for the write mode. the ?ac characteristics? section contains timing specification tables and timing diagrams for write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on dq7?dq0. standard read cycle timings and i cc read specifications apply. refer to ?write operation operation ce# oe# we# reset# (n/a am29f002nb) a0?a17 dq0?dq7 read l l h h a in d out write l h l h a in d in cmos standby v cc 0.5 v x x h x high-z ttl standby h x x h x high-z output disable l h h h x high-z reset (n/a on am29f002nb) x x x l x high-z temporary sector unprotect (see note) xxx v id xx
november 1, 2006 21527d5 am29f002b/am29f002nb 9 data sheet status? for more information, and to each ac charac- teristics section for timing diagrams. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the oe# input. the device enters the cmos standby mode when ce# and reset# pins (ce# only on the am29f002nb) are both held at v cc 0.5 v. (note that this is a more restricted voltage range than v ih .) the device enters the ttl standby mode when ce# and reset# pins (ce# only on the am29f002nb) are both held at v ih . the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. the device also enters the standby mode when the reset# pin is driven low. refer to the next section, ?reset#: hardware reset pin?. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. in the dc characteristics tables, i cc3 represents the standby current specification. reset#: hardware reset pin note: the reset# pin is not available on the am29f002nb. the reset# pin provides a hardware meth od of reset- ting the device to readin g array data. when the system drives the reset# pin low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be rein itiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v il , the device enters the ttl standby mode; if reset# is held at v ss 0.5 v, the device enters the cmos standby mode. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. refer to the ac characteristics tables for reset# parameters and timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high imped- ance state. table 2. am29f002b/am29f002nb top boot block sector address table sector a17 a16 a15 a14 a13 sector size (kbytes) address range (in hexadecimal) sa0 0 0 x x x 64 00000h?0ffffh sa1 0 1 x x x 64 10000h?1ffffh sa2 1 0 x x x 64 20000h?2ffffh sa3 1 1 0 x x 32 30000h?37fffh sa4 1 1 1 0 0 8 38000h?39fffh sa5 1 1 1 0 1 8 3a000h?3bfffh sa6 1 1 1 1 x 16 3c000h?3ffffh
10 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet table 3. am29f002b/am29f002nb bottom boot block sector address table autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on address pin a9. address pins a6, a1, and a0 must be as shown in autoselect codes (high voltage method) table. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the command defini- tions table. this method does not require v id . see ?command definitions? for details on using the autose- lect mode. table 4. am29f002b/am29f002nb autoselect codes (high voltage method) l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hard- ware sector unprotection feature re-enables both program and erase operations in previously protected sectors. sector a17 a16 a15 a14 a13 sector size (kbytes) address range (in hexadecimal) sa0 0 0 0 0 x 16 00000h?03fffh sa1 0 0 0 1 0 8 04000h?05fffh sa2 0 0 0 1 1 8 06000h?07fffh sa3 0 0 1 x x 32 08000h?0ffffh sa4 0 1 x x x 64 10000h?1ffffh sa5 1 0 x x x 64 20000h?2ffffh sa6 1 1 x x x 64 30000h?3ffffh description ce# oe# we# a17 to a13 a12 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq7 to dq0 manufacturer id : amd l l h x x v id x l x l l 01h device id: am29f002b/am29f002nb (top boot block) llh xxv id xlxlh b0h llh device id: am29f002b/am29f002nb (bottom boot block) llh xxv id x l x l h 34h llh sector protection verification l l h sa x v id xlxhl 01h (protected) 00h (unprotected)
november 1, 2006 21527d5 am29f002b/am29f002nb 11 data sheet sector protection/unprotection must be implemented using programming equipment. the procedure requires a high voltage (v id ) on address pin a9 and the control pins. details on this method are provided in the supplements, publication numbers 20819 (am29f002b) and 21183 (am29f002nb). contact an amd representative to obtain a copy of the appropriate document. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is protected or unprotected. see ?autoselect mode? for details. temporary sector unprotect note: this feature requires the reset# pin and is therefore not available on the am29f002nb. this feature allows temporary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly pro- tected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously protected sectors are protected again. figure 1 shows the algo- rithm, and the temporary sector unprotect diagram shows the timing waveforms, for this feature. figure 1. temporary sector unprotect operation hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the command defi- nitions table). in addition, the following hardware data protection measures prevent accidental erasure or pro- gramming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent uninten- tional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to reading array data on power-up. start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again.
12 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet command definitions writing specific address and data commands or sequences into the command register initiates device operations. the command definitions table defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appropriate timing diagrams in the ?ac characteristics? section. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? for more infor- mation on this mode. the system must issue the reset command to re- enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see the ?reset command? section, next. see also ?requirements for reading array data? in the ?device bus operations? section for more information. the read operations table provides the read parame- ters, and read operation timings diagram shows the timing diagram. reset command writing the reset command to the device resets the device to reading array data. address bits are don?t care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manu facturer and devices codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. this method is an alternative to that shown in the autoselect codes (high voltage method) table, which is intended for prom program- mers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h or retrieves the manu- facturer code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. refer to the sector address tables for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. byte program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verify the pro- grammed cell margin. the command definitions take shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using
november 1, 2006 21527d5 am29f002b/am29f002nb 13 data sheet dq7 or dq6. see ?write operation status? for informa- tion on these status bits. any commands written to the device during the embedded program algorithm are ignored. on the am29f002b only, note that a hardware reset during the sector erase operation immediately terminates the operation. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempting to do so may halt the operation and set dq5 to ?1?, or cause the data# polling algorithm to indicate the operation was suc- cessful. however, a succeedin g read will show that the data is still ?0?. only erase operations can convert a ?0? to a ?1?. note: see the appropriate command definitions table for program command sequence. figure 2. program operation chip erase command sequence chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. the command definitions table shows the address and data require- ments for the chip erase command sequence. any commands written to the chip during the embedded erase algorithm are ignored. on the am29f002b only, note that a hardware reset during the sector erase operation immediately terminates the operation. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase oper- ation by using dq7, dq6, or dq2. see ?write operation status? for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 3 illustrates the algorithm for the erase opera- tion. see the erase/program operations tables in ?ac characteristics? for parameters, and to the chip/sector erase operation timings for timing waveforms. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. the start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
14 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see the ?dq3: sector erase timer? section.) the time-out begins from the rising edge of the final we# pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. on the am29f002b only, note that a hard- ware reset during the sector erase operation immediately terminates the operation. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to ?write operat ion status? for information on these status bits. figure 3 illustrates the algorithm for the erase opera- tion. refer to the erase/program operations tables in the ?ac characteristics? section for parameters, and to the sector erase operations timing diagram for timing waveforms. notes: 1. see the appropriate command definitions table for erase command sequence. 2. see ?dq3: sector erase timer? for more information. figure 3. erase operation start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress
november 1, 2006 21527d5 am29f002b/am29f002nb 15 data sheet erase suspend/erase resume commands the erase suspend comma nd allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algo- rithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. addresses are ?don?t-cares? when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately ter- minates the time-out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-sus- pended. see ?write operation status? for information on these status bits. after an erase-suspended program operation is com- plete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program oper- ation. see ?write operation status? for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see ?autoselect command sequence? for more information. the system must write the erase resume command (address bits are ?don?t care?) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing.
16 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet command definitions table 5. am29f002b/am29f002nb command definitions legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a17?a13 uniquely select any sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operations. 4. address bits a17?a11 are don?t cares for unlock and command cycles, except when pa or sa is required. 5. no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 7. the fourth cycle of the autoselect command sequence is a read cycle. 8. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more information. 9. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 10. the erase resume command is valid only during the erase suspend mode. command sequence (note 1) bus cycles (notes 2?4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 auto- select (note 7) manufacturer id 4 555 aa 2aa 55 555 90 x00 01 device id, top boot block 4 555 aa 2aa 55 555 90 x01 b0 device id, bottom boot block 4 555 aa 2aa 55 555 90 x01 34 sector protect verify (note 8) 4 555 aa 2aa 55 555 90 (sa) x02 00 01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 9) 1 xxx b0 erase resume (note 10) 1 xxx 30 cycles
november 1, 2006 21527d5 am29f002b/am29f002nb 17 data sheet write operation status the device provides several bits to determine the status of a write operation: dq2, dq3, dq5, dq6, and dq7. table 6 and the following subsections describe the functions of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase sus- pend. data# polling is valid af ter the rising edge of the final we# pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pr ogram address falls within a protected sector, data# polling on dq7 is active for approximately 2 s, then the device returns to reading array data. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. this is analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to ?1?; prior to this, the device outputs the ?complement,? or ?0.? the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7? dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. the data# polling timings (during embedded algorithms) figure in the ?ac characteristics? section illustrates this. table 6 shows the outputs for data# polling on dq7. figure 4 shows the data# polling algorithm. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 4. data# polling algorithm
18 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycles.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to deter- mine whether a sector is acti vely erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. the write operation status table shows the outputs for toggle bit i on dq6. refer to figure 5 for the toggle bit algorithm, and to the toggle bit timings figure in the ?ac characteristics? section for the timing diagram. the dq2 vs. dq6 figure shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii. dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 6 to compare outputs for dq2 and dq6. figure 5 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the dq6: toggle bit i subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the dq2 vs. dq6 figure shows the dif- ferences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 5 for the following discussion. when- ever the system initially be gins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has com- pleted the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initia l two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog- gling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 5). dq5: exceeded ti ming limits dq5 indicates whether the program or erase time has exceeded a specified intern al pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully completed.
november 1, 2006 21527d5 am29f002b/am29f002nb 19 data sheet the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if addi- tional sectors are selected for erasure, the entire time- out also applies after each additional sector erase com- mand. when the time-out is complete, dq3 switches from ?0? to ?1.? the system may ignore dq3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. see also the ?sector erase command sequence? section. after the sector erase command sequence is written, the system should read the status on dq7 (data# polling) or dq6 (toggle bit i) to ensure the device has accepted the command sequence, and then read dq3. if dq3 is ?1?, the internally controlled erase cycle has begun; all further commands (other than erase sus- pend) are ignored until the erase operation is complete. if dq3 is ?0?, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 6 shows the outputs for dq3. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to ?1?. see text. figure 5. toggle bit algorithm (notes 1, 2) (note 1)
20 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet table 6. write operation status notes: 1. dq7 and dq2 require a valid address when reading status informat ion. refer to the appropriate subsection for further details. 2. dq5 switches to ?1? when an embedded program or embedde d erase operation has exceeded the maximum timing limits. see ?dq5: exceeded timing limits? for more information. operation dq7 (note 1) dq6 dq5 (note 2) dq3 dq2 (note 1) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle embedded erase algorithm 0 toggle 0 1 toggle erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle reading within non-erase suspended sector data data data data data erase-suspend-program dq7# toggle 0 n/a n/a
november 1, 2006 21527d5 am29f002b/am29f002nb 21 data sheet absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . ?55 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . ?2.0 v to +7.0 v a9 , oe# , and reset# (note 2). . . . . . . . . . . .?2.0 v to +12.5 v all other pins (note 1) . . . . . . . . . ?0.5 v to +7.0 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 6. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 7. 2. minimum dc input voltage on pins a9, oe#, and reset# is ?0.5 v. during voltage transitions, a9, oe#, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 6. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to +13.5 v for periods up to 20 ns. (reset# is not available on am29f002nb) 3. no more than one output may be shorted to ground at a time. duration of the short ci rcuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . . 0c to +70c industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c extended (e) devices ambient temperature (t a ) . . . . . . . . ?55c to +125c v cc supply voltages v cc for 5% devices . . . . . . . . . . .+4.75 v to +5.25 v v cc for 10% devices . . . . . . . . . . . .+4.5 v to +5.5 v operating ranges define those li mits between which the func- tionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 6. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 7. maximum positive overshoot waveform
22 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet dc characteristics ttl/nmos compatible notes: 1. reset# is not ava ilable on am29f002nb. 2. maximum i cc specifications are tested with v cc = v ccmax . 3. the i cc current listed is typically le ss than 2 ma/mhz, with oe# at v ih . 4. i cc active while embedded erase or embedded program is in progress. 5. not 100% tested. parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, oe#, reset# input load current (notes 1, 5) v cc = v cc max ; a9, oe#, reset# = 12.5 v 50 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (notes 2, 3) ce# = v il , oe# = v ih 20 30 ma i cc2 v cc active write current (n otes 2, 4, 5) ce# = v il , oe# = v ih 30 40 ma i cc3 v cc standby current (note 2) ce#, oe# = v ih 0.4 1 ma i cc4 v cc reset current (not es 1, 2) reset# = v il 0.4 1 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v id voltage for autoselect and temporary sector unprotect v cc = 5.0 v 11.5 12.5 v v ol output low voltage i ol = 12 ma, v cc = v cc min 0.45 v v oh output high voltage i oh = ?2.5 ma, v cc = v cc min 2.4 v v lko low v cc lock-out voltage 3.2 4.2 v
november 1, 2006 21527d5 am29f002b/am29f002nb 23 data sheet dc characteristics cmos compatible notes: 1. reset# is not ava ilable on am29f002nb. 2. maximum i cc specifications are tested with v cc = v ccmax . 3. the i cc current listed is typically le ss than 2 ma/mhz, with oe# at v ih . 4. i cc active while embedded erase or embedded program is in progress. 5. not 100% tested. 6. i cc3 and i cc4 = 20 a max at extended temperature (>+85 c). parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, oe#, reset# input load current (notes 1, 5) v cc = v cc max ; a9, oe#, reset# = 12.5 v 50 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (notes 2, 3) ce# = v il , oe# = v ih 20 30 ma i cc2 v cc active write current (notes 2, 4, 5) ce# = v il , oe# = v ih 30 40 ma i cc3 v cc standby current (notes 2, 6) ce# = v cc 0.5 v 1 5 a i cc4 v cc reset current (notes 1, 2, 6) reset# = v il 15a v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v id voltage for autoselect and temporary sector unprotect v cc = 5.0 v 11.5 12.5 v v ol output low voltage i ol = 12 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?2.5 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage 3.2 4.2 v
24 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet test conditions table 7. test specifications key to switching waveforms 2.7 k c l 6.2 k 5.0 v device under te s t figure 8. test setup note: diodes are in3064 or equivalent test condition -55 all others unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 20 ns input pulse levels 0.0?3.0 0.45?2.4 v input timing measurement reference levels 1.5 0.8, 2.0 v output timing measurement reference levels 1.5 0.8, 2.0 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z)
november 1, 2006 21527d5 am29f002b/am29f002nb 25 data sheet ac characteristics read operations notes: 1. not 100% tested. 2. see table 7 and figure 8 for test specifications. parameter description speed options jedec std test setup -55 -70 -90 unit t avav t rc read cycle time (note 1) min 55 70 90 ns t avqv t acc address to output delay ce# = v il oe# = v il max557090ns t elqv t ce chip enable to output delay oe# = v il max557090ns t glqv t oe output enable to output delay max 30 30 35 ns t ehqz t df chip enable to output high z (note 1) max 15 20 20 ns t ghqz t df output enable to output high z (note 1) max152020ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 1) min 0 ns t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe reset# n/a am29f002nb t df t oh figure 9. read operations timings
26 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet ac characteristics hardware reset (reset#) note: not 100% tested. reset# is not available on am29f002nb. parameter description all speed options jedec std test setup unit t ready reset# pin low (during embedded algorithms) to read or write (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read (see note) min 50 ns reset# n/a am29f002nb t rp t ready reset timings not during embedded algorithms ce#, oe# t rh reset timings during embedded algorithms reset# n/a am29f002nb t rp figure 10. reset# timings
november 1, 2006 21527d5 am29f002b/am29f002nb 27 data sheet ac characteristics erase/program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter speed options jedec std description -55 -70 -90 unit t avav t wc write cycle time (note 1) min 55 70 90 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 45 45 45 ns t dvwh t ds data setup time min 25 30 45 ns t whdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 30 35 45 ns t whwl t wph write pulse width high min 20 ns t whwh1 t whwh1 programming operation (note 2) typ 7 s t whwh2 t whwh2 sector erase operation (note 2) typ 1 sec t vcs v cc setup time (note 1) min 50 s
28 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) t ch pa notes: 1. pa = program address, pd = program data, d out is the true data at the program address. figure 11. program operation timings
november 1, 2006 21527d5 am29f002b/am29f002nb 29 data sheet ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (?see ?write operation status?). figure 12. chip/sector erase operation timings
30 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet ac characteristics we# ce# oe# high z t oe high z dq7 dq0?dq6 complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle af ter command sequence, last stat us read cycle, and array data read cycle. figure 13. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe dq6/dq2 addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. figure 14. toggle bit timings (during embedded algorithms)
november 1, 2006 21527d5 am29f002b/am29f002nb 31 data sheet ac characteristics temporary sector un protect (am29f002b only) note: not 100% tested. parameter all speed options jedec std. description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s note: the system may use ce# or oe# to toggle dq2 and dq 6. dq2 toggles only when read at an address within an erase-suspended sector. figure 15. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing reset# t vidr 12 v 0 or 5 v ce# we# ry/by# t vidr t rsp program or erase command sequence 0 or 5 v figure 16. temporary sector unprotect timing diagram (am29f002b only)
32 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet ac characteristics alternate ce# cont rolled erase/pr ogram operations 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter speed options jedec std. description -55 -70 -90 unit t avav t wc write cycle time (note 1) min 55 70 90 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 45 45 ns t dveh t ds data setup time min 25 30 45 ns t ehdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 30 35 45 ns t ehel t cph ce# pulse width high min 20 ns t whwh1 t whwh1 programming operation (note 2) typ 7 s t whwh2 t whwh2 sector erase operation (note 2) typ 1 sec
november 1, 2006 21527d5 am29f002b/am29f002nb 33 data sheet ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase notes: 1. pa = program address, pd = program data, dq7# = complement of data written to device, d out = data written to device. 2. figure indicates the last two bus cycles of the command sequence. figure 17. alternate ce# controlled write operation timings
34 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25c, 5.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 4.5 v (4.75 v for 5% devices), 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maxi mum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the four-bus-cycle sequence for the program command. see table 5 for further information on command definitions. 6. the device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 5.0 v, one pin at a time. r eset# not availabl e on am29f002nb. tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 1 8 s excludes 00h programming prior to erasure (note 4) chip erase time 7 s byte programming time 7 300 s excludes system level overhead (note 5) chip programming time (note 3) 1.8 5.4 s description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf
november 1, 2006 21527d5 am29f002b/am29f002nb 35 data sheet plcc and pdip pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. data retention parameter symbol parameter description test conditions typ max unit c in input capacitance v in = 0 4 6 pf c out output capacitance v out = 0 8 12 pf c in2 control pin capacitance v pp = 0 8 12 pf parameter test conditions min unit minimum pattern data retention time 150 c10 years 125 c20 years
36 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet physical dimensions pd 032?32-pin plastic dip dwg rev ad; 10/99
november 1, 2006 21527d5 am29f002b/am29f002nb 37 data sheet physical dimensions (continued) pl 032?32-pin plastic leaded chip carrier dwg rev ah; 10/99
38 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet physical dimensions (continued) ts 032?32-pin standard thin small package dwg rev aa; 10/99
november 1, 2006 21527d5 am29f002b/am29f002nb 39 data sheet revision summary revision a (july 1998) initial release. revision b (january 1999) distinctive characteristics added: 20-year data retention at 125 c ? reliable operation for the life of the system ac characterisitics?read operations table t ehqz , t ghqz : changed the 55 speed option to 15 ns from 20 ns ac characteristics?erase/program operations t wlax : changed the 90 speed option to 45 ns from 50 ns. t dvwh : changed the 55 speed option to 25 ns from 30 ns. t wlwh : changed the 55 speed option to 30 ns from 35 ns. ac characteristics?alternate ce# controlled erase/program operations t dveh : changed the 55 speed option to 25 ns from 30 ns. t eleh : changed the 55 speed option to 30 ns from 35 ns. t elax : changed the 90 speed option to 45 ns from 50 ns. dc characteristics?ttl/nmos compatible i cc1 , i cc2 , i cc3 , i cc4 : added note 2 ?maximum i cc specifications are tested with v cc = v ccmax ?. dc characteristics? cmos compatible i cc1 , i cc2 , i cc3 , i cc4 : added note 2 ?maximum i cc specifications are tested with v cc = v ccmax ?. revision c (november 12, 1999) ac characteristics?figure 11. program operations timing and figure 12. chip/sector erase operations deleted t ghwl and changed oe# waveform to start at high. physical dimensions replaced figures with more detailed illustrations. revision d (november 28, 2000) global added table of contents. ordering information deleted burn-in option. table 5, command definitions in note 4, changed the lower address bit of don?t care range to a11. revision d +1 (november 5, 2004) ordering information and valid combinations added pb-free options revision d +2 (august 3, 2005) ordering information and valid combinations added pb-free options revision d3 (december 13, 2005) global deleted 120 ns speed option. revision d4 (may 17, 2006) added ?not recommended for new designs? note. revision d5 (november 1, 2006) deleted ?not recommended for new designs? note.
40 am29f002b/am29f002nb 21527d5 november 1, 2006 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limita- tion, ordinary industrial use, general o ffice use, personal use, and household use, but are not designed, developed and manufac tured as con- templated (1) for any use that includes fatal risks or dangers th at, unless extremely high safety is secured, could have a seri ous effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor de- vices have an inherent chance of failure. y ou must protect against injury, damage or loss from such failures by incorporating s afety design mea- sures into your facility and equipment such as redundancy, fire protection, and prevention of ov er-current levels and other abn ormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on expor t under the foreign exchange and foreign trade law of japan, the us export administra tion regulations or the applicable laws of any other country, the prior au- thorization by the respective government entit y will be required for export of those products. trademarks copyright ? 2006 spansion inc. all rights reserved. spansion, the spansion logo, mirrorbit, orna nd, hd-sim, and combinations th ereof, are trademarks of spansion inc. other company and product names used in this publication are for identification purposes only and m ay be trade- marks of their respective companies. copyright ? 1998?2005 advanced micro devices, inc. all rights reserv ed. amd, the amd logo, and combinations thereof are registe red trade- marks of advanced micro devices, inc. expressflash is a trademar k of advanced micro devices, inc. product names used in this pu blication are for identification purposes only and may be tr ademarks of their respective companies

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